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| october 2004 i ? 2004 actel corporation see actel?s website for the latest version of the datasheet radtolerant fpgas features general characteristics ? tested total ionizing dose (tid) survivability level no single event latch-up below a minimum let (linear energy transfer) threshold of 80 mev-cm 2 /mg for all rt (radtolerant) devices packages: 84-pin, 132-pin, 172-pin, 196-pin, and 256-pin ceramic quad flat pack offered as class b and e-flow (actel space level flow) qml certified devices 100% military temper ature tested (?55c to +125c) high density and performance 4,000 to 20,000 logic equivalent gates 2,000 to 10,000 asic equivalent gates up to 85 mhz internal performance up to 60 mhz system performance up to 228 user i/os up to four fast, low-skew clock networks easy logic integration nonvolatile, user programmable pin-compatible commercial devices available for prototyping highly predictable performance with 100% automatic place-and-route 100% resource utilization with 100% pin-locking secure programming technol ogy prevents reverse engineering and design theft permanently programmed for operation on power-up unique in-system diagnostic and verification capability with silicon explorer product family profile table 1 radtolerant family device rt1020 rt1280a rt1425a rt1460a rt14100a capacity system gates logic gates asic equivalent gates pld equivalent gates ttl equivalent package 20-pin pal equivalent packages 6,000 4,000 2,000 5,000 50 20 24,000 16,000 8.000 20,000 200 80 7,500 5,000 2,500 6,250 60 25 18,000 12,000 6,000 15.000 150 60 30,000 20,000 10,000 25,000 250 100 logic modules s-modules c-modules 547 n/a 547 1,232 624 608 310 160 150 848 432 416 1,377 697 680 user i/os (maximum) 69 140 100 168 228 performance system speed (maximum) 20 mhz 40 mhz 60 mhz 60 mhz 60 mhz packages (by pin count) cqfp 84 172 132 196 256 v3.1
radtolerant fpgas ii v3.1 ordering information device resources contact your actel sales represen tative for product availability. part number speed grade package type package lead count application (temperature range) rt1280a e cq - 172 cq = ceramic quad flat pack (cqfp) c = commercial (0 to +70?c) m = military (-55 to +125?c) b = mil-std-883 class b e = extended flow (space level) rt1020 = 4,000 gates?radtolerant act 1 rt1280a = 16,000 gates?radtolerant act 2 rt1425a = 5,000 gates?radtolerant act 3 rt1460a = 12,000 gates?radtolerant act 3 rt14100a = 20,000 gates?radtolerant act 3 a1020b = 4,000 gates?act 1 a1280a = 16,000 gates?act 2 a1425a = 5,000 gates?act 3 a1460a = 12,000 gates?act 3 a14100a = 20,000 gates?act 3 std = standard speed -1 = approximately 15% faster than standard fpga device type logic modules gate array equivalent gates user i/os cqfp 84-pin cqfp 132-pin cqfp 172-pin cqfp 196-pin cqfp 256-pin rt1020/a1020b 547 2,000 69 ? ? ? ? rt1280a/a1280a 1,232 8,000 ? ? 140 ? ? rt1425a/a1425a 310 2,500 ? 100 ? ? ? rt1460a/a1460a 848 6,000 ? ? ? 168 ? rt14100a/a14100a 1,377 10,000 ? ? ? ? 228 note: package definition: cqfp = ceramic quad flat pack radtolerant fpgas v3.1 iii product plan speed grade application std ?1* commercial mil itary mil-std-883 extended flow act 1 rt1020 device 84-pin ceramic quad flat pack (cqfp) ? ?? ? ?? a1020b device (prototyping use) 84-pin ceramic quad flat pack (cqfp) ????? ? act 2 rt1280a device 172-pin ceramic quad flat pack (cqfp) ?? ?? ?? a1280a device (prototyping use) 172-pin ceramic quad flat pack (cqfp) ????? ? act 3 rt1425a device 132-pin ceramic quad flat pack (cqfp) ?? ?? ?? a1425a device (prototyping use) 132-pin ceramic quad flat pack (cqfp) ????? ? rt1460a device 196-pin ceramic quad flat pack (cqfp) ?? ?? ?? a1460a device (prototyping use) 196-pin ceramic quad flat pack (cqfp) ????? ? rt14100a device 256-pin ceramic quad flat pack (cqfp) ?? ?? ?? a14100a device (prototyping use) 256-pin ceramic quad flat pack (cqfp) ????? ? note: contact your actel sales re presentative for product av ailability. availability: ? = available, ? symbol = not planned * speed grade: ?1 = approx. 15% faster than standard iv v3.1 table of contents radtolerant fpgas radtolerant fpgas general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 radiation survivability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 qml certification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 development tool support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 radtolerant architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 logic modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1- 2 the rt1020 logic module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 parameter measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 sequential timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15 rt1020, a1020b timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17 rt1280a, a1280a timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19 rt1425a, a1425a timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22 rt1460a, a1460a timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25 rt14100a, a14100a timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31 package pin assignments 84-pin cqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 132-pin cqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 -3 172-pin cqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 -6 196-pin cqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 -9 256-pin cqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2 datasheet information list of changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 -1 datasheet categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 export administration regulations (ear ) or international traffic in arms regulations (itar) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 radtolerant fpgas v3.1 1-1 radtolerant fpgas general description actel builds the most reliable field programmable gate arrays (fpgas) in the industry, with overall antifuse reliability ratings of less th an 10 failures-in-time (fits), corresponding to a useful life of more than 40 years. actel fpgas are production-proven, with more than five million devices shipped and more than one trillion antifuses manufactured. actel devices are fully tested prior to shipment, with an outgoing defect level of only 122 ppm (further reliability data is available in the actel device reliability report ) . additionally, the programmable architecture of these devices offers high performance, design flexibility, and fast and inexpensive prototyping?all without the expense of test vectors, nre charges, long lead times, and schedule and cost penalties for design refinements. device description the rt1020 device contains the same architecture as the a1020, a1020a, and a1020b devices. the architecture, a combinatorial logic module, is a logic structure with 8 inputs and 1 output. the logi c itself is comprised of a 4-input mux, as described in figure 1-3 on page 1-4 . in addition, since the rt1020 device contains the same number of gates and i/os and has the same operating voltage as its commercial equivalent (a1020b), an in expensive comme rcial grade a1020b-cq84 device can be used during the prototype phase, and replaced by the rt1020 in the flight units. the rt1280a device uses the a1280a die from the act 2 family of fpgas. it utilizes a two-module architecture, consisting of combinatoria l modules (c-modules) and sequential modules (s-modules) optimized for both combinatorial and sequential designs. based on actel?s patented channeled array architecture, the rt1280a has 8,000 asic-equivalent gates and 140 user i/os. the rt1280a device is fully pi n- and function-compatible with the commercially-equivalent a1280a-cq172c device for easy, inexpensive prototyping. the rt1425a, rt1460a and rt14100a devices use the a1425a, a1460a and a14100a dies, respectively. these devices are derived from the act 3 family of fpgas, which also utilizes the two-module channeled array architecture, and offers faster performance than the rt1280a. these devices also have fully pin- and function- compatible commercially-equiv alent devices for easy and inexpensive prototyping. th e a1425a-cq132c is used for the rt1425a, the a1460a-cq196c is used for the rt1460a, and the a14100a-cq256c is used for the rt14100a. radiation survivability total dose results are summarized in two ways. the first method summarizes by the maximum total dose level that is reached when the parts fail to meet a device specification but remain functional. for actel fpgas, the parameter that exceeds the specification first is the standby supply current (i cc ). the second method summarizes by the maximum total dose that is reached prior to the functional failure of the device. the actel rt devices have varying total-dose radiation survivability. the ability of these devices to survive radiation effects is both device- and lot-dependent. the user must evaluate and determine the applicability of these devices for specific design and environmental requirements. typical results for the rt1020 device are ~100krads (si) for standby i cc and >100krads for functional failure. the rt1280a device has results from 4 to 10krads (si) for standby i cc , and 7 to 18krads for functional failure. typical results for act 3 devices are 10 to 28krads for i cc , and 20 to 77krads for functional failure. actel will provide total dose radiation testing along with the test data on each pedigreed lot that is available for sale. these reports are availa ble on our website, or you can contact your local sales representative to receive a copy. a listing of available lots and devices is also provided. these results are pr ovided only for reference and for customer information. for a radiation performance summary, see radiation performance of actel products on the actel website. this summary also shows single event upset (seu) and single event latch-up (sel) testing that has been performed on actel fpgas. radtolerant fpgas 1-2 v3.1 qml certification actel has achieved full qml ce rtification, demonstrating that quality management, pr ocedures, processes, and controls are in place and co mply with mil-prf-38535, the performance specification used by the department of defense for monolithic integrated circuits. qml certification is an exampl e of actel's commitment to supplying the highest quality products for all types of high-reliability, military and space applications. many suppliers of microelectronics components have implemented qml as their primary worldwide business system. appropriate use of th is system not only helps in the implementation of advanced technologies, but also allows for quality, reliable an d cost-effective logistics support throughout the qml products life cycles. disclaimer all radiation performance in formation is provided for information purposes only and is not guaranteed. the total dose effects are lot-dependent, and actel does not guarantee that future device s will continue to exhibit similar radiation characteristics. in addition, actual performance can vary widely due to a variety of factors, including but not limited to characteristics of the orbit, radiation environment, prox imity to satellite exterior, amount of inherent shielding from other sources within the satellite, and actual bare die variations. for these reasons, actel does not guara ntee any level of radiation survivability, and it is sole ly the responsibility of the customer to determ ine whether the device will meet the requirements of the specific design. development tool support t he hirel devices are fully supported by both the actel libero? integrated design environment (ide) and designer fpga development software. actel libero ide is a design management environment, seamlessly integrating design tools while guiding the user through the design flow, managing all design and log files, and passing necessary design data among tools. libero ide allows users to integrate both schematic and hdl synthesis into a single flow and verify the entire design in a single environment. li bero ide includes synplify ? for actel from synplicity ? , viewdraw ? for actel from mentor graphics, model sim ? hdl simulator from mentor graphics ? , waveformer lite? from synapticad?, and designer software from actel. refer to the libero ide flow diagram for more information. actel's designer software is a place-and-route tool and provides a comprehensive su ite of backend support tools for fpga development. the designer software includes timing-driven place-and-r oute, and a world-class integrated static timing analyzer and constraints editor. with the designer software, a user can select and lock package pins while only mini mally impacting the results of place-and-route. additionally , the back-annotation flow is compatible with all the major simulators and the simulation results can be cross- probed with silicon explorer ii, actel?s integrated verifica tion and logic analysis tool. another tool included in the designer software is the actgen macro builder, which easily creates popular and commonly used logic functions for implementation into your schematic or hdl design. actel's designer software is compatible with the most popular fpga design entry and verification tools from companies such as mentor graphics, synplicity, synopsys, and ca dence design systems. the designer software is availa ble for both the windows and unix operating systems. radtolerant architecture the actel architecture is comp osed of fine-grained logic modules that produce fast, efficient logic designs. all devices are composed of logic modules, routing resources, clock networks, and i/o modules, which are the building blocks for fast logic designs. logic modules these radtolerant devices contain two types of logic modules, combinatorial (c-modules) and sequential (s-modules). rt1020 and a1020b devices contain only c- modules. the c-module, shown in figure 1-1 , implements eq 1-1 : y = !s1*!s0*d00+!s1*s0*d01+s1*!s0*d10+s1*s0*d11 eq 1-1 where: s0 = a0 * b0 s1 = a1+ b1 figure 1-1 c-module implementation d00 d01 d10 d11 s0 s1 y a0 b0 a1 b1 radtolerant fpgas v3.1 1-3 the s-module, shown in figure 1-2 , is designed to implement high-speed sequential functions within a single logic module. the s-module implements the same combinatorial logic function as the c-module while adding a sequential element. the sequential element can be configured as either a d-type flip-flop or a transparent latch. to increa se flexibility, the s-module register can be bypassed so it implements purely combinatorial logic. flip-flops can also be created using two c-modules. the seu characteristics differ be tween an s-module flip-flop and a flip-flop created using two c-modules. for details see the design techniques for radhard field programmable gate arrays application note. figure 1-2 s-module implementation d11 d01 d00 d10 y out s1 s0 up to 7-input function plus d-type flip-flop with clear d11 d01 d00 d10 y s1 s0 up to 7-input function plus latch y up to 4-input function plus latch with clear d11 d01 d00 d10 yout s1 s0 up to 8-input function (same as c-module) s d1 d0 clr dq out clr dq out gate dq gate radtolerant fpgas 1-4 v3.1 the rt1020 logic module the rt1020 logic module is an 8-input, 1-output logic circuit chosen for the wide range of functions it implements and for its effi cient use of interconnect routing resources ( figure 1-3 ). the logic module can implement the four basic logic functions (nand, and, or, and nor) in gates of two, three, or four inputs. each function may have many versions, with different co mbinations of active low inputs. the logic module can also implement a variety of d-latches, exclusivity functions, and-ors, and or-ands. no dedicated hardwired latches or flip-flops are required in the array, since latches and flip-flops may be constructed from logic module s wherever needed in the application. i/o modules i/o modules provide the interface between the device pins and the logic array. a variety of user functions, determined by a library macro selection, can be implemented in the m odule (refer to the macro library guide for more information) . i/o modules contain a tristate buffer, and input and output latches that can be configured for input, output, or bidirectional pins ( figure 1-4 ). the radtolerant devices contai n flexible i/o structures in that each output pin has a dedicated output enable control. the i/o module can be used to latch input and/or output data, providing a fast setup time. in addition, the actel designer software tools can build a d-flip-flop, using a c-module, to register input and/or output signals. the actel designer software development tools provide a design library of i/o macros. the i/o macro library provides macro functions that can implement all i/o configurations supported by the radtolerant fpgas. routing structure the radtolerant device archit ecture uses vertical and horizontal routing tracks to interconnect the various logic and i/o modules. these routing tracks are metal interconnects that may either be of continuous length or broken into segments. varying segment lengths allow over 90% of the circuit interconnects to be made with only two antifuse connections. segments can be joined together at the ends, using antifuses to increase their length up to the full length of the track. all interconnects can be accomplished with a maximum of four antifuses. horizontal routing horizontal channels are lo cated between the rows of modules, and are composed of several routing tracks. the horizontal routing trac ks within the channel are divided into one or more segments. the minimum horizontal segment length is the width of a module-pair, and the maximum horizontal segment length is the full length of the channel. an y segment that spans more than one-third the row le ngth is considered a long horizontal segment. a typical channel is shown in figure 1-5 on page 1-5 . non-dedicated horizontal routing tracks are used to route signal nets. dedicated routing tracks are used for the global clock networks, and for power and ground tie-off tracks. vertical routing another set of routing tracks runs vertically through the module. there are three types of vertical tracks that can be divided into one or more segments: input, output, and long. each segment in an input track is dedicated to the input of a particular module. each segment in an figure 1-3 rt1020 logic module figure 1-4 i/o module g/clk* qd en pa d * can be configured as a latch or d-flip-flop from array to array (using c-module) g/clk* qd radtolerant fpgas v3.1 1-5 output track is dedicated to the output of a particular module. long segments are uncommitted and can be assigned during routing. each output segment spans four channels (two above and two below), except near the top and bottom of the array where edge effects occur. long vertical tracks contain either one or two segments. an example of ve rtical routing tracks and segments is shown in figure 1-5 . antifuse structures an antifuse is a "normally open" structure as opposed to the normally closed fuse structure used in proms (programmable read-only memory) or pals (programmed array logic). the use of an tifuses to implement a pld (programmable logic device) results in highly testable structures, as well as efficient programming algorithms. the structure is highly testa ble because there are no pre- existing connections, enabling temporary connections to be made using pass transistors. these temporary connections can isolate individual antifuses to be programmed, and also isolate individual circuit structures to be tested. this can be done both before and after programming. for example, all metal tracks can be tested for continuity and shorts between adjacent tracks, and the functionality of all logic modules can be verified. figure 1-5 routing structure vertical routing tracks segmented horizontal routing tracks logic modules antifuses table 1-1 actel mil-std-883 product flow step screen 883 method 883 - class b requirement 1. internal visual 2010, test condition b 100% 2. temperature cycling 1010, test condition c 100% 3. constant acceleration 2001, test condition d or e, y 1 , orientation only 100% 4. seal a. fine b. gross 1014 100% 100% 5. visual inspection 2009 100% 6. pre-burn-in electrical parameters in accordance with applicable actel device specification 100% 7. burn-in test 1015, condition d, 160 hours @ 125c or 80 hours @ 150c 100% 8. interim (post-burn-in) electrical parameters in accordance with applicable actel device specification 100% 9. percent defective allowable 5% all lots 10. final electrical test a. static tests (1) 25c (subgroup 1, table i) (2) ?55c and +125c (subgroups 2, 3, table i) b. functional tests (1) 25c (subgroup 7, table i) (2) ?55c and +125c (subgroups 8a and 8b, table i) c. switching tests at 25c (subgroup 9, table i) in accordance with applicable ac tel device specification, which includes a, b, and c: 5005 5005 5005 5005 5005 100% 100% 100% 11. external visual 2009 100% note: when destructive physical analysis (dpa) is performed on class b devices, the step co verage requirement as specified in method 2018 must be waived. radtolerant fpgas 1-6 v3.1 table 1-2 actel extended flow 1 step screen method requirement 1. wafer lot acceptance 2 5007 with step coverage waiver all lots 2. destructive in-line bond pull 3 2011, condition d sample 3. internal visual 2010, condition a 100% 4. serialization 100% 5. temperature cycling 1010, condition c 100% 6. constant acceleration 2001, condition d or e, y 1 orientation only 100% 7. particle impact noise detection 2020, condition a 100% 8. radiographic 2012 100% 9. pre-burn-in test in accordance with ap plicable actel device specification 100% 10. burn-in test 1015, condition d, 240 hours @ 125c minimum 100% 11. interim (post-burn-in) electrical parameters in accord ance with applicable actel device specification 100% 12. reverse bias burn-in 1015, condition c, 72 hours @ 150c minimum 100% 13. interim (post-burn-in) electrical parameters in accord ance with applicable actel device specification 100% 14. percent defective allowable (pda) calculation 5%, 3% functional parameters @ 25c all lots 15. final electrical test a. static tests (1) 25c (subgroup 1, table1) (2) ?55c and +125c (subgroups 2, 3, table 1) b. functional tests (1) 25c (subgroup 7, table 15) (2) ?55c and +125c (subgroups 8a and b, table 1) c. switching tests at 25c (subgroup 9, table 1) in accordance with actel app licable device specification, which includes a, b, and c: 5005 5005 5005 5005 5005 100% 100% 100% 100% 16. seal a. fine b. gross 1014 100% 17. external visual 2009 100% notes: 1. actel offers the extended flow for custom ers that require additional screening beyo nd the requirements of mil-std-883, class b . actel is compliant to the requirements of mil-std-883, paragraph 1.2.1, and mil-i- 38535, appendix a. actel is offering this extended flow incorporating the majority of the screening proc edures as outlined in method 5004 of mil-std-883 class s. the exceptions to method 5004 are shown in notes 2 and 3 below. 2. wafer lot acceptance is performed to meth od 5007; however, the step coverage requir ement as specified in method 2018 must be waived. 3. method 5004 requires a 100 percent, non-destructive bond pull (method 2023). actel substitutes a destructive bond pull (method 2011), condition d on a sample basis only. radtolerant fpgas v3.1 1-7 absolute maximum ratings stresses beyond those listed in this table may cause permanent damage to the device. exposure to absolute maximum rated conditions for extended periods may affect device reliability. de vices should not be operated outside the recommended operating conditions. table 1-3 free air temperature range symbol parameter limits units v cc dc supply voltage 1, 2, 3 ?0.5 to +7.0 v v i input voltage ?0.5 to v cc +0.5 v v o output voltage ?0.5 to v cc +0.5 v i io i/o source sink current 4 20 ma t stg storage temperature ?65 to +150 c notes: 1. v pp = v cc , except during device programming 2. v sv = v cc , except during device programming 3. v ks = gnd, except during device programming 4. device inputs are normally high impedanc e and draw extremely low current. however, when input voltage is greater than v cc + 0.5 v or less than gnd ? 0.5 v, the internal protection diode will be forward-biased and can draw excessive current. table 1-4 recommended operating conditions parameter commercial military units temperature range 1 0 to +70 ?55 to +125 c power supply tolerance 2 5 10 %v cc notes: 1. ambient temperature (t a ) is used for commercial and industrial; case temperature (t c ) is used for military 2. all power supplies must be in the recommended oper ating range. for more information, refer to the power-up and power-down behavior of 54sx and rt54sx devices application note. table 1-5 electrical specifications symbol parameter test condition commercial military units min. max. min. max. v oh 1, 2 high level output i oh = ?4 ma (cmos) 3.7 v i oh = ?6 ma (cmos) 3.84 v v ol 1, 2 low level output i ol = +6 ma (cmos) 0.33 0.4 v v ih high level input ttl inputs 2.0 v cc + 0.3 2.0 v cc + 0.3 v v il low level input ttl inputs ?0.3 0.8 ?0.3 0.8 v i in input leakage v i = v cc or gnd ?10 +10 ?10 +10 a i oz 3-state output leakage v o = v cc or gnd ?10 +10 ?10 +10 a c io i/o capacitance 3, 4 10 10 pf i cc(s) standby v cc supply current v i = v cc or gnd, i o = 0 ma 2 20 ma i cc(d) dynamic v cc supply current see "power dissipation" on page 1-8 . notes: 1. actel devices can drive and receive either cmos or ttl signal levels. no assignment of i/os as ttl or cmos is required. 2. tested one output at a time, v cc = min. 3. not tested; for information only 4. v out = 0v, f = 1 mhz radtolerant fpgas 1-8 v3.1 package thermal characteristics the device junction to case thermal characteristic is jc , and the junction to ambien t air characteristic is ja . the thermal characteristics for ja are shown with two different air flow rates. maximum junction temperature is 150c. a sample calculation of the absolute maximum power dissipation allowed for a cqfp 172-pin package at military temperature is as follows: eq 1-2 power dissipation general power equation p = [i cc standby + i cc active] * v cc + i ol * v ol * n + i oh * (v cc ? v oh ) * m eq 1-3 where: i cc standby is the current flowing when no inputs or outputs are changing. i cc active is the current flowing due to cmos switching. i ol , i oh are ttl sink/source currents. v ol , v oh are ttl level output voltages. n equals the number of outputs driving ttl loads to v ol . m equals the number of outputs driving ttl loads to v oh . accurate values for n and m are difficult to determine because they depend on the family type, on design details, and on the system i/o. the power can be divided into two components: static and active. static power component actel fpgas have small static power components that result in power dissipation lower than that of pals or plds. by integratin g multiple pals or plds into one fpga, an even greater redu ction in board-level power dissipation can be achieved. the power due to standby cu rrent is typically a small component of the overall power. standby power is calculated below for commerci al, worst-case conditions. the static power dissipated by ttl loads depends on the number of outputs driving high or low and on the dc load current. again, this value is typically small. for instance, a 32-bit bus sinking 4 ma at 0.33 v will generate 42 mw with all outputs driving low, and 140 mw with all outputs driving high. table 1-6 package thermal characteristics package type pin count jc ja still air ja 300 ft./min. units ceramic quad flat pack 8 7.8 40 30 c/w 132 7.2 35 25 c/w 172 6.8 25 20 c/w 196 6.4 23 15 c/w 256 6.2 20 10 c/w max. junction temp. (c) ? max. military temp. ja c/w () ---------------------------------------------------------------------------------------------------------------------- - 150c ? 125c 25c/w -------------------------------------- -1.0w == i cc v cc power 2 ma 5.25 v 10.5 mw radtolerant fpgas v3.1 1-9 active power component power dissipation in cmos devices is usually dominated by the active (dynamic) power dissipation. this component is frequency-dependent, a function of the logic and the external i/o. active power dissipation results from charging internal chip capacitances of the interconnect, unprogrammed antifuses, module inputs, and module outputs, plus external capacitance due to pc board traces and load device inputs. an additional component of the active power dissipation is the totem pole current in cmos transistor pairs. the net effect can be associated with an equiva lent capacitance that can be combined with frequency and voltage to represent active power dissipation. equivalent capacitance the power dissipated by a cmos circuit can be expressed by eq 1-4 : power (uw) = c eq * v cc 2 * f eq 1-4 where: equivalent capacitance is calculated by measuring i cc active at a specified frequency and voltage for each circuit component of interest. meas urements are made over a range of frequencies at a fixed value of v cc . equivalent capacitance is frequency-inde pendent, so the results can be used over a wide ra nge of operating conditions. equivalent capacitance values are shown in table 1-7 . c eq = equivalent capacitance in pf v cc = power supply in volts (v) f = switching frequency in mhz table 1-7 ceq values for actel fpgas rt1020, a1020b rt1280a, a1280a rt1425a, a1425a, rt1460a, a1460a, rt14100a, a14100a modules (c eqm )3.7 5.8 6.7 input buffers (c eqi ) 22.1 12.9 7.2 output buffers (c eqo ) 32.1 23.8 10.4 routed array clock buffer loads (c eqcr )4.6 3.9 1.6 dedicated clock buffer loads (c eqcd ) n/a n/a 0.7 i/o clock buffer loads (c eqci ) n/a n/a 0.9 radtolerant fpgas 1-10 v3.1 to calculate the active power dissipated from the complete design, the switching frequency of each part of the logic must be known. eq 1-5 shows a piece-wise linear summation over all components. since the rt1280a and a1280a have two routed array clocks, the dedicated_clk and io_clk terms do not apply. for all other devices all terms apply. power = v cc 2 * [(m * c eqm * f m ) modules + (n * c eqi * f n ) inputs + (p * (c eqo + c l ) * f p ) outputs + 0.5 * (q 1 * c eqcr * f q1 ) routed_clk1 + (r 1 *f q1 ) routed_clk1 + 0.5 * (q 2 * c eqcr * f q2 ) routed_clk2 + (r 2 * f q2 ) routed_clk2 + 0.5 * (s 1 * c eqcd * f s1 ) dedicated_clk + (s 2 * c eqci * f s2 ) io_clk ] eq 1-5 where: m = number of logic modules switching at f m n = number of input buffers switching at f n p = number of output buffers switching at f p q 1 = number of clock loads on the first routed array clock q 2 = number of clock loads on the second routed array clock (not applicable for rt1020 or a1020b) r 1 = fixed capacitance due to first routed array clock r 2 = fixed capacitance due to second routed array clock (not applicable for rt1020 or a1020b) s 1 = fixed number of clock loads on the dedicated array clock (not applicable for rt1020, a1020b, rt1280a, or a1280a) s 2 = fixed number of clock loads on the dedicated i/o clock (not applicable for rt1020, a1020b, rt1280a, or a1280a) c eqm = equivalent capacitance of logic modules in pf c eqi = equivalent capacitance of input buffers in pf c eqo = equivalent capacitance of output buffers in pf c eqcr = equivalent capacitance of routed array clock in pf c eqcd = equivalent capacitance of dedicated array clock in pf c eqci = equivalent capacitance of dedicated i/o clock in pf c l = output lead capacitance in pf f m = average logic module switching rate in mhz f n = average input buffer switching rate in mhz f p = average output buffer switching rate in mhz f q1 = average first routed array clock rate in mhz f q2 = average second routed array clock rate in mhz (not applicable for rt1020 or a1020b) f s1 = average dedicated array clock rate in mhz (not applicable for rt1020, a1020b, rt1280a, or a1280a) f s2 = average dedicated i/o clock rate in mhz (not applicable for rt1020, a1020b, rt1280a, or a1280a) table 1-8 fixed capacitance values for actel fpgas (pf) device type r 1 routed_clk1 r 2 routed_clk2 rt1020, a1020b 69 n/a rt1280a, a1280a 168 168 rt1425a, a1425a 75 75 rt1460a, a1460a 165 165 rt14100a, a14100a 195 195 table 1-9 fixed clock loads (s1/s2 ? act 3 only) device type s 1 clock loads on dedicated array clock s 2 clock loads on dedicated i/o clock rt1425a, a1425a 160 100 rt1460a, a1460a 432 168 rt14100a, a14100a 697 228 radtolerant fpgas v3.1 1-11 determining average switching frequency to determine the switching frequency for a design, you must have a detailed understanding of the data input values to the circuit. the guidelines below are m eant to represent worst-case scenarios; they can be generally used to predict the upper limits of power dissipation. rt1020, a1020b, rt1280a, a1280a rt1425a, a1425a, rt1460a, a1460a, rt14100a, a14100a logic modules (m) = 80% of combinatorial modules input switching (n) = # inputs/4 outputs switching (p) = # outputs/4 first routed array clock loads (q 1 ) = 40% of sequential modules second routed array clock loads (q 2 ) = 40% of sequential modules load capacitance (c l ) = 35 pf average logic module switching rate (f m )=f/10 average input switching rate (f n )=f/5 average output switching rate (f p )=f/10 average first routed array clock rate (f q1 )=f average second routed array clock rate (f q2 )=f/2 average dedicated array clock rate (f s1 )=n/a average dedicated i/o clock rate (f s2 )=n/a logic modules (m) = 80% of combinatorial modules input switching (n) = # inputs/4 outputs switching (p) = # outputs/4 first routed array clock loads (q 1 ) = 40% of sequential modules second routed array clock loads (q 2 ) = 40% of sequential modules load capacitance (c l )=35 pf average logic module switching rate (f m )=f/10 average input switching rate (f n )=f/5 average output switching rate (f p )=f/10 average first routed array clock rate (f q1 )=f/2 average second routed array clock rate (f q2 )=f/2 average dedicated array clock rate (f s1 )=f average dedicated i/o clock rate (f s2 )=f radtolerant fpgas 1-12 v3.1 figure 1-6 rt1020, a1020b timing model notes: 1. *values shown for rt1280a ?1 at worst-case military conditions. 2. ? input module predicted routing delay figure 1-7 rt1280a, a1280a timing model* t ird1 = 1.1 ns t ird4 = 3.9 ns t ird8 = 8.1 ns t pd = 3.6 ns t co = 3.6 ns output delay input delay i/o module logic module i/o module array clock predicted ro uti ng delays fo = 128 internal delays t rd1 = 1.1 ns t rd2 = 1.8 ns t rd4 = 3.9 ns t rd8 = 8.1 ns t enhz = 12.3 ns t dlh = 8.3 ns t ird2 = 1.9 ns t inyl = 3.9 ns t ckh = 6.9 ns f max = 55 mhz t inyl = 3.6 ns t inh = 2.5 ns t insu = 3.5 ns t ingl = 6.6 ns output delays input delays i/o module dq ? internal delays sequential logic module i/o module i/o module array clocks dq dq predicted ro uti ng delays g g fo = 32 t ird2 = 7.2 ns t pd1 = 5.2 ns t rd1 = 2.4 ns t rh2 = 3.4 ns t rd4 = 5.1 ns t rd8 = 9.2 ns t dlh = 14.0 ns t dlh = 14.0 ns f max = 73 mhz t ckh = 13.3 ns t sud = 0.5 ns t hd = 0.0 ns t co = 5.2 ns t rd1 = 2.4 ns t outh = 0.0 ns t outsu = 0.5 ns t glh = 12.5 ns t enhz = 9.8 ns combin- atorial logic included in t sud combinatorial logic module radtolerant fpgas v3.1 1-13 note: *values shown for rt14100a ?1 at worst-case military conditions. figure 1-8 rt1425a, a1425a, rt1460a, a1460a, rt14100a, a14100a timing model* i/o clock f iomax = 100 mhz t iockh = 3.5 ns (pad-to-pad) combinatorial logic included in t sud dq t iny = 4.2 ns output delays input delays i/o module combinatorial logic module i/o module array clock dq predicted ro uti ng delays t ird2 = 1.9 ns t pd = 3.0 ns t rd1 = 1.3 ns t rd4 = 2.6 ns t rd8 = 4.2 ns t dhs = 9.2 ns f hmax = 100 mhz t hckh = 5.5 ns t co = 3.0 ns t rd1 = 1.3 ns t enzhs = 7.7 ns internal delays t su = 1.0 ns t hd = 0.6 ns t dhs = 9.2 ns t inh = 0.0 ns t insu = 2.1 ns t icky = 7.0 ns sequential logic module i/o module t outh = 1.2 ns t outsu = 1.2 ns t ckhs = 14.4 ns dq radtolerant fpgas 1-14 v3.1 parameter measurement figure 1-9 output buffer delays figure 1-10 ac test load to ac test loads (shown below) pad d e tribuff in 50% pa d 1.5v 50% 1.5v e 50% pa d 1.5v 50% 10% e 50% pa d gnd 1.5v 50% 90% t dlh t dhl t enzl t enlz t enzh t enhz v oh v oh v cc v cc v cc gnd gnd gnd v cc v ol v ol load 1 (used to measure propagation delay) load 2 (used to measure rising/falling edges) 50 pf to the output under test ? v cc gnd to the output under test 50 pf r to v cc for t plz/ t pzl r to gnd for t phz/ t pzh r = 1 k figure 1-11 input buffer delays pa d y inbuf pa d 3v 0v 1.5v y gnd v cc 50% t inyh 1.5v 50% t inyl figure 1-12 combinatorial macro delays s a b y s, a or b y 50% t plh y 50% 50% 50% 50% 50% t phl t phl t plh v cc gnd gnd v cc gnd v cc radtolerant fpgas v3.1 1-15 sequential timing characteristics d represents all data functions involvin g a, b, and s for mu ltiplexed flip-flops. figure 1-13 flip-flops and latches (rt1280a, a1280a) d represents all data functions involvin g a, b, and s for mu ltiplexed flip-flops. figure 1-14 flip-flops and latches (rt1425a, a142 5a, rt1460a, a1460a, rt14100a, a14100a) t rs (positive edge triggered) d clk clr pre y d 1 g, clk q pre, clr t wclka t wasyn t hd t sud t a t t hena suena t co e e t clr (positive edge triggered) d clk clr preset y d 1 g, clk q clr t wclka t wasyn t hd t sud t a t t hena suena t co e e radtolerant fpgas 1-16 v3.1 figure 1-15 input buffer latches (r1280a, a1280a) figure 1-16 output buffer latches (rt1280a, a1280a) clk g pad ibdl pad g t inh t insu clk t hext t suext pad clkbuf d g pad obdlhs d g t outsu t outh radtolerant fpgas v3.1 1-17 rt1020, a1020b timing characteristics table 1-10 rt1020, a1020b logic and input modules worst-case military conditions, v cc = 4.5 v, t j = 125c std speed parameter description min. max. units logic module propagation delays t pd1 single module 3.6 ns t pd2 dual module macros 8.4 ns t co sequential clock to q 3.6 ns t go latch g to q 3.6 ns t rs flip-flop (latch) reset to q 3.6 ns logic module predicted routing delays 1 t rd1 fo=1 routing delay 1.1 ns t rd2 fo=2 routing delay 1.8 ns t rd3 fo=3 routing delay 2.6 ns t rd4 fo=4 routing delay 3.9 ns t rd8 fo=8 routing delay 8.1 ns logic module sequential timing 2 t sud flip-flop (latch) data input setup 6.9 ns t hd 3 flip-flop (latch) data input hold 0.0 ns t suena flip-flop (latch) enable setup 6.9 ns t hena flip-flop (latch) enable hold 0.0 ns t wclka flip-flop (latch) clock active pulse width 8.4 ns t wasyn flip-flop (latch) asynchronous pulse width 8.4 ns t a flip-flop clock input period 17.5 ns f max flip-flop (latch) clock frequency (fo = 128) 55 mhz input module propagation delays t inyh pad to y high 3.9 ns t inyl pad to y low 3.9 ns input module predicted routing delays 1, 3 t ird1 fo=1 routing delay 1.1 ns t ird2 fo=2 routing delay 1.8 ns t ird3 fo=3 routing delay 2.6 ns t ird4 fo=4 routing delay 3.9 ns t ird8 fo=8 routing delay 8.1 ns notes: 1. routing delays are for typical designs ac ross worst-case operating co nditions. these parameters sh ould be used for estimating device performance. post-route timing analysis or simulation is required to determin e actual worst-case performance. post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 2. setup times assume fanout of 3. further testing information can be obtained from the timer utility. 3. optimization techniques may furt her reduce delays by 0 to 4ns. 4. the hold time for the dfme1a macro may be greater than 0ns. us e the designer software 3.0 (or later) timer to check the hold time for this macro. radtolerant fpgas 1-18 v3.1 table 1-11 rt1020, a1020b output module worst-case milita ry conditions, v cc = 4.5 v, t j = 125c std speed parameter description min. max. units global clock network t ckh input low to high fo = 16 fo = 128 6.0 6.9 ns t ckl input high to low fo = 16 fo = 128 7.9 8.7 ns t pwh minimum pulse width high fo = 16 fo = 128 8.0 8.4 ns t pwl minimum pulse width low fo = 16 fo = 128 1.5 2.2 ns t cksw maximum skew fo = 16 fo = 128 1.5 2.3 ns t p minimum period fo = 16 fo = 128 16.3 17.5 ns f max maximum frequency fo = 16 fo = 128 60 50 mhz ttl output module timing 1 t dlh data to pad high 8.3 ns t dhl data to pad low 9.3 ns t enzh enable pad z to high 8.1 ns t enzl enable pad z to low 9.8 ns t enhz enable pad high to z 12.3 ns t enlz enable pad low to z 11.1 ns d tlh delta low to high 0.07 ns/pf d thl delta high to low 0.10 ns/pf cmos output module timing 1 t dlh data to pad high 9.8 ns t dhl data to pad low 7.9 ns t enzh enable pad z to high 7.4 ns t enzl enable pad z to low 10.2 ns t enhz enable pad high to z 12.3 ns t enlz enable pad low to z 11.1 ns d tlh delta low to high 0.13 ns/pf d thl delta high to low 0.07 ns/pf notes: 1. delays based on 35pf loading. 2. sso information can be found in the simultaneously switching output limits for actel fpgas application note. radtolerant fpgas v3.1 1-19 rt1280a, a1280a timing characteristics table 1-12 rt1280a, a1280a logic module worst-case military conditions, v cc = 4.5 v, t j = 125c ?1 speed std speed parameter description min. max. min. max. units logic module propagation delays 1 t pd1 single module 5.2 6.1 ns t co sequential clock-to-q 5.2 6.1 ns t go latch g-to-q 5.2 6.1 ns t rs flip-flop (latch) reset-to-q 5.2 6.1 ns logic module predicted routing delays 2 t rd1 fo=1 routing delay 2.4 2.8 ns t rd2 fo=2 routing delay 3.4 4.0 ns t rd3 fo=3 routing delay 4.2 4.9 ns t rd4 fo=4 routing delay 5.1 6.0 ns t rd8 fo=8 routing delay 9.2 10.8 ns logic module sequential timing 3, 4 t sud flip-flop (latch) data input setup 0.5 0.5 ns t hd flip-flop (latch) data input hold 0.0 0.0 ns t suena flip-flop (latch) enable setup 1.3 1.3 ns t hena flip-flop (latch) enable hold 0.0 0.0 ns t wclka flip-flop (latch) clock ac tive pulse width 7.4 8.6 ns t wasyn flip-flop (latch) asynchronous pulse width 7.4 8.6 ns t a flip-flop clock input period 16.4 22.1 ns t inh input buffer latch hold 2.5 2.5 ns t insu input buffer latch setup 3.5 3.5 ns t outh output buffer latch hold 0.0 0.0 ns t outsu output buffer latch setup 0.5 0.5 ns f max flip-flop (latch) clock frequency 60 41 mhz notes: 1. for dual-module macros, use t pd1 + t rd1 + t pdn , t co + t rd1 + t pdn , or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs ac ross worst-case operating co nditions. these parameters sh ould be used for estimating device performance. post-route timing analysis or simulation is required to determin e actual worst-case performance. post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 3. data applies to macros based on the s-module. timing para meters for sequential macros constructed from c-modules can be obtained from the timer utility. 4. setup and hold timing parameters for the input buffer latch are defined with respec t to the pad and the d input. external set up/ hold timing parameters must account for dela y from an external pad signal to the g inputs. delay from an external pad signal to the g input subtracts (adds) to the internal setup (hold) time. radtolerant fpgas 1-20 v3.1 table 1-13 rt1280a, a1280a input module worst-case military conditions, v cc = 4.5 v, t j = 125c ?1 speed std speed parameter description mi n. max. min. max. units input module propagation delays t inyh pad-to-y high 4.0 4.7 ns t inyl pad-to-y low 3.6 4.3 ns t ingh g-to-y high 6.9 8.1 ns t ingl g-to-y low 6.6 7.7 ns input module predicted routing delays 1 t ird1 fo=1 routing delay 6.2 7.3 ns t ird2 fo=2 routing delay 7.2 8.4 ns t ird3 fo=3 routing delay 7.7 9.1 ns t ird4 fo=4 routing delay 8.9 10.5 ns t ird8 fo=8 routing delay 12.9 15.2 ns global clock network t ckh input low to high fo = 32 fo = 384 13.3 17.9 15.7 21.1 ns t ckl input high to low fo = 32 fo = 384 13.3 18.2 15.7 21.4 ns t pwh minimum pulse width high fo = 32 fo = 384 6.9 7.9 8.1 9.3 ns t pwl minimum pulse width low fo = 32 fo = 384 6.9 7.9 8.1 9.3 ns t cksw maximum skew fo = 32 fo = 384 0.6 3.1 0.6 3.1 ns t suext input latch external setup fo = 32 fo = 384 0.0 0.0 0.0 0.0 ns t hext input latch external hold fo = 32 fo = 384 8.6 13.8 8.6 13.8 ns t p minimum period fo = 32 fo = 384 13.7 16.0 16.2 18.9 ns f max maximum frequency fo = 32 fo = 384 73 63 62 53 mhz note: 1. routing delays are for typical designs ac ross worst-case operating co nditions. these parameters sh ould be used for estimating device performance. post-route timing analysis or simulation is required to determin e actual worst-case performance. post-route timing is based on actual routing delay measurements performed on the device prior to shipment. optimization techniques may further reduce delays by 0 to 4ns. radtolerant fpgas v3.1 1-21 table 1-14 rt1280a, a1280a output module worst-case military conditions, v cc = 4.5 v, t j = 125c ?1 speed std speed parameter description min. max. min. max. units ttl output module timing 1 t dlh data-to-pad high 11.0 13.0 ns t dhl data-to-pad low 13.9 16.4 ns t enzh enable-to-pad z to high 12.3 14.4 ns t enzl enable-to-pad z to low 16.1 19.0 ns t enhz enable-to-pad high to z 9.8 11.5 ns t enlz enable-to-pad low to z 11.5 13.6 ns t glh g-to-pad high 12.4 14.6 ns t ghl g-to-pad low 15.5 18.2 ns d tlh delta low to high 0.09 0.11 ns/pf d thl delta high to low 0.17 0.20 ns/pf cmos output module timing 1 t dlh data-to-pad high 14.0 16.5 ns t dhl data-to-pad low 11.7 13.7 ns t enzh enable-to-pad z to high 12.3 14.4 ns t enzl enable-to-pad z to low 16.1 19.0 ns t enhz enable-to-pad high to z 9.8 11.5 ns t enlz enable-to-pad low to z 11.5 13.6 ns t glh g-to-pad high 12.4 14.6 ns t ghl g-to-pad low 15.5 18.2 ns d tlh delta low to high 0.17 0.20 ns/pf d thl delta high to low 0.12 0.15 ns/pf notes: 1. delays based on 50pf loading. 2. sso information can be found in the simultaneously switching output limits for actel fpgas application note. radtolerant fpgas 1-22 v3.1 rt1425a, a1425a timing characteristics table 1-15 rt1425a, a1425a logic and input modules worst-case military conditions, v cc = 4.5 v, t j = 125c ?1 speed std speed parameter description min. max. min. max. units logic module propagation delays 1 t pd internal array module 3.0 3.5 ns t co sequential clock to q 3.0 3.5 ns t clr asynchronous clear to q 3.0 3.5 ns logic module predicted routing delays 2 t rd1 fo=1 routing delay 1.3 1.5 ns t rd2 fo=2 routing delay 1.9 2.1 ns t rd3 fo=3 routing delay 2.1 2.5 ns t rd4 fo=4 routing delay 2.6 2.9 ns t rd8 fo=8 routing delay 4.2 4.9 ns logic module sequential timing t sud flip-flop (latch) data input setup 0.9 1.0 ns t hd flip-flop (latch) data input hold 0.0 0.0 ns t suena flip-flop (latch) enable setup 0.9 1.0 ns t hena flip-flop (latch) enable hold 0.0 0.0 ns t wasyn asynchronous pulse width 3.8 4.4 ns t wclka flip-flop clock pulse width 3.8 4.4 ns t a flip-flop clock input period 7.9 9.3 ns f max flip-flop clock frequency 125 100 mhz input module propagation delays t iny input data pad to y 4.2 4.9 ns t icky input reg ioclk pad to y 7.0 8.2 ns t ocky output reg ioclk pad to y 7.0 8.2 ns t iclry input asynchronous clear to y 7.0 8.2 ns t oclry output asynchronous clear to y 7.0 8.2 ns input module predicted routing delays 2, 3 t ird1 fo=1 routing delay 1.3 1.5 ns t ird2 fo=2 routing delay 1.9 2.1 ns t ird3 fo=3 routing delay 2.1 2.5 ns t ird4 fo=4 routing delay 2.6 2.9 ns t ird8 fo=8 routing delay 4.2 4.9 ns notes: 1. for dual-module macros, use t pd + t rd1 + t pdn , t co + t rd1 + t pdn , or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs ac ross worst-case operating co nditions. these parameters sh ould be used for estimating device performance. post-route timing analysis or simulation is required to determin e actual worst-case performance. post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 3. optimization techniques may furt her reduce delays by 0 to 4ns. radtolerant fpgas v3.1 1-23 table 1-16 rt1425a, a1425a logic and input modules worst-case military conditions, v cc = 4.5 v, t j = 125c ?1 speed std speed parameter description mi n. max. min. max. units i/o module sequential timing t inh input f-f data hold (w.r.t. ioclk pad) 0.0 0.0 ns t insu input f-f data setup (w.r.t. ioclk pad) 2.1 2.4 ns t ideh input data enable hold (w.r.t. ioclk pad) 0.0 0.0 ns t idesu input data enable setup (w.r.t. ioclk pad) 8.7 10.0 ns t outh output f-f data hold (w.r.t. ioclk pad) 1.1 1.2 ns t outsu output f-f data setup (w.r.t. ioclk pad) 1.1 1.2 ns t odeh output data enable hold (w.r.t. ioclk pad) 0.5 0.6 ns t odesu output data enable setup (w.r.t. ioclk pad) 2.0 2.4 ns ttl output module timing 1 t dhs data to pad, high slew 7.5 8.9 ns t dls data to pad, low slew 11.9 14.0 ns t enzhs enable to pad, z to h/ l, high slew 6.0 7.0 ns t enzls enable to pad, z to h/ l, low slew 10.9 12.8 ns t enhsz enable to pad, h/l to z, high slew 9.9 11.6 ns t enlsz enable to pad, h/l to z, low slew 9.9 11.6 ns t ckhs ioclk pad to pad h/l, high slew 10.5 11.6 ns t ckls ioclk pad to pad h/l, low slew 15.7 17.4 ns d tlhhs delta low to high, high slew 0.04 0.04 ns/pf d tlhls delta low to high, low slew 0.07 0.08 ns/pf d thlhs delta high to low, high slew 0.05 0.06 ns/pf d thlls delta high to low, low slew 0.07 0.08 ns/pf cmos output module timing 1 t dhs data to pad, high slew 9.2 10.8 ns t dls data to pad, low slew 17.3 20.3 ns t enzhs enable to pad, z to h/ l, high slew 7.7 9.1 ns t enzls enable to pad, z to h/ l, low slew 13.1 15.5 ns t enhsz enable to pad, h/l to z, high slew 9.9 11.6 ns t enlsz enable to pad, h/l to z, low slew 10.5 11.6 ns t ckhs ioclk pad to pad h/l, high slew 12.5 13.7 ns t ckls ioclk pad to pad h/l, low slew 18.1 20.1 ns d tlhhs delta low to high, high slew 0.06 0.07 ns/pf d tlhls delta low to high, low slew 0.11 0.13 ns/pf d thlhs delta high to low, high slew 0.04 0.05 ns/pf d thlls delta high to low, low slew 0.05 0.06 ns/pf note: 1. delays based on 35pf loading. radtolerant fpgas 1-24 v3.1 table 1-17 rt1425a, a1425a clock networks worst-case military conditions, v cc = 4.5 v, t j = 125c ?1 speed std speed parameter description min. max. min. max. units dedicated (hard-wired) i/o clock network t iockh input low to high (pad to i/o module input) 3.0 3.5 ns t iopwh minimum pulse width high 3.9 4.4 ns t iopwl minimum pulse width low 3.9 4.4 ns t iosapw minimum asynchronous pulse width 3.9 4.4 ns t iocksw maximum skew 0.5 0.5 ns t iop minimum period 7.9 9.3 ns f iomax maximum frequency 125 100 mhz dedicated (hard-wired) array clock network t hckh input low to high (pad to s-module input) 4.6 5.3 ns t hckl input high to low (pad to s-module input) 4.6 5.3 ns t hpwh minimum pulse width high 3.9 4.4 ns t hpwl minimum pulse width low 3.9 4.4 ns t hcksw maximum skew 0.4 0.4 ns t hp minimum period 7.9 9.3 ns f hmax maximum frequency 125 100 mhz routed array clock networks t rckh input low to high (fo=64) 5.5 6.4 ns t rckl input high to low (fo=64) 6.0 7.0 ns t rpwh minimum pulse width high (fo=64) 4.9 5.7 ns t rpwl minimum pulse width low (fo=64) 4.9 5.7 ns t rcksw maximum skew (fo=128) 1.1 1.2 ns t rp minimum period (fo=64) 10.1 11.6 ns f rmax maximum frequency (fo=64) 100 85 mhz clock-to-clock skews t iohcksw i/o clock to h-clock skew 0.0 3.0 0.0 3.0 ns t iorcksw i/o clock to r-clock skew 0.0 3.0 0.0 3.0 ns t hrcksw h-clock to r-clock skew (fo = 64) (fo = 50% max.) 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 ns ns note: sso information can be found in the simultaneously switching out put limits for actel fpgas application note. radtolerant fpgas v3.1 1-25 rt1460a, a1460a timing characteristics table 1-18 rt1460a, a1460a logic and input modules worst-case military conditions, v cc = 4.5 v, t j = 125c ?1 speed std speed parameter description min. max. min. max. units logic module propagation delays 1 t pd internal array module 3.0 3.5 ns t co sequential clock to q 3.0 3.5 ns t clr asynchronous clear to q 3.0 3.5 ns logic module predicted routing delays 2 t rd1 fo=1 routing delay 1.3 1.5 ns t rd2 fo=2 routing delay 1.9 2.1 ns t rd3 fo=3 routing delay 2.1 2.5 ns t rd4 fo=4 routing delay 2.6 2.9 ns t rd8 fo=8 routing delay 4.2 4.9 ns logic module sequential timing t sud flip-flop (latch) data input setup 0.9 1.0 ns t hd flip-flop (latch) data input hold 0.0 0.0 ns t suena flip-flop (latch) enable setup 0.9 1.0 ns t hena flip-flop (latch) enable hold 0.0 0.0 ns t wasyn asynchronous pulse width 4.8 5.6 ns t wclka flip-flop clock pulse width 4.8 5.6 ns t a flip-flop clock input period 9.9 11.6 ns f max flip-flop clock frequency 100 85 mhz input module propagation delays t iny input data pad to y 4.2 4.9 ns t icky input reg ioclk pad to y 7.0 8.2 ns t ocky output reg ioclk pad to y 7.0 8.2 ns t iclry input asynchronous clear to y 7.0 8.2 ns t oclry output asynchronous clear to y 7.0 8.2 ns predicted input routing delays 2, 3 t ird1 fo=1 routing delay 1.3 1.5 ns t ird2 fo=2 routing delay 1.9 2.1 ns t ird3 fo=3 routing delay 2.1 2.5 ns t ird4 fo=4 routing delay 2.6 2.9 ns t ird8 fo=8 routing delay 4.2 4.9 ns notes: 1. for dual-module macros, use t pd + t rd1 + t pdn , t co + t rd1 + t pdn , or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs ac ross worst-case operating co nditions. these parameters sh ould be used for estimating device performance. post-route timing analysis or simulation is required to determin e actual worst-case performance. post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 3. optimization techniques may furt her reduce delays by 0 to 4ns. radtolerant fpgas 1-26 v3.1 table 1-19 rt1460a, a1460a i/o and output modules worst-case military conditions, v cc = 4.5 v, t j = 125c ?1 speed std speed parameter description min. max. min. max. units i/o module sequential timing t inh input f-f data hold (w.r.t. ioclk pad) 0.0 0.0 ns t insu input f-f data setup (w.r.t. ioclk pad) 2.1 2.4 ns t ideh input data enable hold (w.r.t. ioclk pad) 0.0 0.0 ns t idesu input data enable setup (w.r.t. ioclk pad) 8.7 10.0 ns t outh output f-f data hold (w.r.t. ioclk pad) 1.1 1.2 ns t outsu output f-f data setup (w.r.t. ioclk pad) 1.1 1.2 ns t odeh output data enable hold (w.r.t. ioclk pad) 0.5 0.6 ns t odesu output data enable setup (w.r.t. ioclk pad) 2.0 2.4 ns ttl output module timing 1 t dhs data to pad, high slew 7.5 8.9 ns t dls data to pad, low slew 11.9 14.0 ns t enzhs enable to pad, z to h/l, high slew 6.0 7.0 ns t enzls enable to pad, z to h/ l, low slew 10.9 12.8 ns t enhsz enable to pad, h/l to z, high slew 11.5 13.5 ns t enlsz enable to pad, h/l to z, low slew 10.9 12.8 ns t ckhs ioclk pad to pad h/l, high slew 11.6 13.4 ns t ckls ioclk pad to pad h/l, low slew 17.8 19.8 ns d tlhhs delta low to high, high slew 0.04 0.04 ns/pf d tlhls delta low to high, low slew 0.07 0.08 ns/pf d thlhs delta high to low, high slew 0.05 0.06 ns/pf d thlls delta high to low, low slew 0.07 0.08 ns/pf cmos output module timing 1 t dhs data to pad, high slew 9.2 10.8 ns t dls data to pad, low slew 17.3 20.3 ns t enzhs enable to pad, z to h/l, high slew 7.7 9.1 ns t enzls enable to pad, z to h/ l, low slew 13.1 15.5 ns t enhsz enable to pad, h/l to z, high slew 10.9 12.8 ns t enlsz enable to pad, h/l to z, low slew 10.9 12.8 ns t ckhs ioclk pad to pad h/l, high slew 14.1 16.0 ns t ckls ioclk pad to pad h/l, low slew 20.2 22.4 ns d tlhhs delta low to high, high slew 0.06 0.07 ns/pf d tlhls delta low to high, low slew 0.11 0.13 ns/pf d thlhs delta high to low, high slew 0.04 0.05 ns/pf d thlls delta high to low, low slew 0.05 0.06 ns/pf note: 1. delays based on 35pf loading. radtolerant fpgas v3.1 1-27 table 1-20 rt1460a, a1460a clock networks worst-case military conditions, v cc = 4.5 v, t j = 125c ?1 speed std speed parameter description min. max. min. max. units dedicated (hard-wired) i/o clock network t iockh input low to high (pad to i/o module input) 3.5 4.1 ns t iopwh minimum pulse width high 4.8 5.7 ns t iopwl minimum pulse width low 4.8 5.7 ns t iosapw minimum asynchronous pulse width 3.9 4.4 ns t iocksw maximum skew 0.9 1.0 ns t iop minimum period 9.9 11.6 ns f iomax maximum frequency 100 85 mhz dedicated (hard-wired) array clock network t hckh input low to high (pad to s-module input) 5.5 6.4 ns t hckl input high to low (pad to s-module input) 5.5 6.4 ns t hpwh minimum pulse width high 4.8 5.7 ns t hpwl minimum pulse width low 4.8 5.7 ns t hcksw maximum skew 0.9 1.0 ns t hp minimum period 9.9 11.6 ns f hmax maximum frequency 100 85 mhz routed array clock networks t rckh input low to high (fo=256) 9.0 10.5 ns t rckl input high to low (fo=256) 9.0 10.5 ns t rpwh min. pulse width high (fo=256) 6.3 7.1 ns t rpwl min. pulse width low (fo=256) 6.3 7.1 ns t rcksw maximum skew (fo=128) 1.9 2.1 ns t rp minimum period (fo=256) 12.9 14.5 ns f rmax maximum frequency (fo=256) 75 65 mhz clock-to-clock skews t iohcksw i/o clock to h-clock skew 0.0 3.0 0.0 3.0 ns t iorcksw i/o clock to r-clock skew 0.0 5.0 0.0 5.0 ns t hrcksw h-clock to r-clock skew (fo = 64) (fo = 50% max.) 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 ns ns note: sso information can be found in the simultaneously switching out put limits for actel fpgas application note. radtolerant fpgas 1-28 v3.1 rt14100a, a14100a timing characteristics table 1-21 rt14100a, a14100a logic and input modules worst-case military conditions, v cc = 4.5 v, t j = 125c ?1 speed std speed parameter description min. max. min. max. units logic module propagation delays 1 t pd internal array module 3.0 3.5 ns t co sequential clock-to-q 3.0 3.5 ns t clr asynchronous clear-to-q 3.0 3.5 ns logic module predicted routing delays 2 t rd1 fo=1 routing delay 1.3 1.5 ns t rd2 fo=2 routing delay 1.9 2.1 ns t rd3 fo=3 routing delay 2.1 2.5 ns t rd4 fo=4 routing delay 2.6 2.9 ns t rd8 fo=8 routing delay 4.2 4.9 ns logic module sequential timing t sud flip-flop (latch) data input setup 1.0 1.0 ns t hd flip-flop (latch) data input hold 0.6 0.6 ns t suena flip-flop (latch) enable setup 1.0 1.0 ns t hena flip-flop (latch) enable hold 0.6 0.6 ns t wasyn asynchronous pulse width 4.8 5.6 ns t wclka flip-flop clock pulse width 4.8 5.6 ns t a flip-flop clock input period 9.9 11.6 ns f max flip-flop clock frequency 100 85 mhz input module propagation delays t iny input data pad-to-y 4.2 4.9 ns t icky input reg ioclk pad-to-y 7.0 8.2 ns t ocky output reg ioclk pad-to-y 7.0 8.2 ns t iclry input asynchronous clear-to-y 7.0 8.2 ns t oclry output asynchronous clear-to-y 7.0 8.2 ns input module predicted routing delays 2, 3 t ird1 fo=1 routing delay 1.3 1.5 ns t ird2 fo=2 routing delay 1.9 2.1 ns t ird3 fo=3 routing delay 2.1 2.5 ns t ird4 fo=4 routing delay 2.6 2.9 ns t ird8 fo=8 routing delay 4.2 4.9 ns notes: 1. for dual-module macros, use t pd + t rd1 + t pdn , t co + t rd1 + t pdn , or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs ac ross worst-case operating co nditions. these parameters sh ould be used for estimating device performance. post-route timing analysis or simulation is required to determin e actual worst-case performance. post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 3. optimization techniques may furt her reduce delays by 0 to 4ns. radtolerant fpgas v3.1 1-29 table 1-22 rt14100a, a14100a i/o and output modules worst-case military conditions, v cc = 4.5 v, t j = 125c ?1 speed std speed parameter description min. max. min. max. units i/o module sequential timing t inh input flip-flop data hold 0.0 0.0 ns t insu input flip-flop data setup 2.1 2.4 ns t ideh input data enable hold 0.0 0.0 ns t idesu input data enable setup 8.7 10.0 ns t outh output flip-flop data hold 1.2 1.2 ns t outsu output flip-flop data setup 1.2 1.2 ns t odeh output data enable hold 0.6 0.6 ns t odesu output data enable setup 2.4 2.4 ns ttl output module timing 1 t dhs data-to-pad, high slew 7.5 8.9 ns t dls data-to-pad, low slew 11.9 14.0 ns t enzhs enable-to-pad, z to h/l, high slew 6.0 7.0 ns t enzls enable-to-pad, z to h/l, low slew 10.9 12.8 ns t enhsz enable-to-pad, h/l to z, high slew 11.9 14.0 ns t enlsz enable-to-pad, h/l to z, low slew 10.9 12.8 ns t ckhs ioclk pad-to-pad h/l, high slew 12.2 14.0 ns t ckls ioclk pad-to-pad h/l, low slew 17.8 17.8 ns d tlhhs delta low to high, high slew 0.04 0.04 ns/pf d tlhls delta low to high, low slew 0.07 0.08 ns/pf d thlhs delta high to low, high slew 0.05 0.06 ns/pf d thlls delta high to low, low slew 0.07 0.08 ns/pf cmos output module timing 1 t dhs data-to-pad, high slew 9.2 10.8 ns t dls data-to-pad, low slew 17.3 20.3 ns t enzhs enable-to-pad, z to h/l, high slew 7.7 9.1 ns t enzls enable-to-pad, z to h/l, low slew 13.1 15.5 ns t enhsz enable-to-pad, h/l to z, high slew 11.6 14.0 ns t enlsz enable-to-pad, h/l to z, low slew 10.9 12.8 ns t ckhs ioclk pad-to-pad h/l, high slew 14.4 16.0 ns t ckls ioclk pad-to-pad h/l, low slew 20.2 22.4 ns d tlhhs delta low to high, high slew 0.06 0.07 ns/pf d tlhls delta low to high, low slew 0.11 0.13 ns/pf d thlhs delta high to low, high slew 0.04 0.05 ns/pf d thlls delta high to low, low slew 0.05 0.06 ns/pf note: 1. delays based on 35 pf loading. radtolerant fpgas 1-30 v3.1 table 1-23 rt14100a, a14100a clock networks worst-case military conditions, v cc = 4.5 v, t j = 125c ?1 speed std speed parameter description min. max. min. max. units dedicated (hard-wired) i/o clock network t iockh input low to high (pad to i/o module input) 3.5 4.1 ns t iopwh minimum pulse width high 4.8 5.7 ns t iopwl minimum pulse width low 4.8 5.7 ns t iosapw minimum asynchronous pulse width 3.9 4.4 ns t iocksw maximum skew 0.9 1.0 ns t iop minimum period 9.9 11.6 ns f iomax maximum frequency 100 85 mhz dedicated (hard-wired) array clock network t hckh input low to high (pad to s-module input) 5.5 6.4 ns t hckl input high to low (pad to s-module input) 5.5 6.4 ns t hpwh minimum pulse width high 4.8 5.7 ns t hpwl minimum pulse width low 4.8 5.7 ns t hcksw maximum skew 0.9 1.0 ns t hp minimum period 9.9 11.6 ns f hmax maximum frequency 100 85 mhz routed array clock networks t rckh input low to high (fo=256) 9.0 10.5 ns t rckl input high to low (fo=256) 9.0 10.5 ns t rpwh min. pulse width high (fo=256) 6.3 7.1 ns t rpwl min. pulse width low (fo=256) 6.3 7.1 ns t rcksw maximum skew (fo=128) 1.9 2.1 ns t rp minimum period (fo=256) 12.9 14.5 ns f rmax maximum frequency (fo=256) 75 65 mhz clock-to-clock skews t iohcksw i/o clock to h-clock skew 0.0 3.5 0.0 3.5 ns t iorcksw i/o clock to r-clock skew 0.0 5.0 0.0 5.0 ns t hrcksw h-clock to r-clock skew (fo = 64) (fo = 50% max.) 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 ns note: sso information can be found in the simultaneously switching out put limits for actel fpgas application note. radtolerant fpgas v3.1 1-31 pin descriptions clk clock (input) rt1020 and a1020b only. ttl clock input for global clock distribution networks. the clock input is buffered prior to clocking the logic modules. this pin can also be used as an i/o. clka clock a (input) not applicable for rt1020 an d a1020b. ttl clock input for global clock distribution networks. the clock input is buffered prior to clocking th e logic modules. this pin can also be used as an i/o. clkb clock b (input) not applicable for rt1020 an d a1020b. ttl clock input for global clock distribution networks. the clock input is buffered prior to clocking th e logic modules. this pin can also be used as an i/o. dclk diagnostic clock (input) ttl clock input for diagnostic probe and device programming. dclk is acti ve when the mode pin is high. this pin functions as an i/o when the mode pin is low. gnd ground low supply voltage. hclk dedicated (hard-wired) array clock (input) not applicable for rt1020, a1020b, rt1280a and a1280a. ttl clock input for sequential modules. this input is directly wired to each s-module, offering clock speeds independent of the nu mber of s-modules being driven. this pin can also be used as an i/o. i/o input/output (input, output) i/o pin functions as an in put, output, tristate, or bidirectional buffer. input and output levels are compatible with standard ttl and cmos specifications. in the rt1020, a1020b, rt1280, and a1280a devices, unused i/o pins are automatically driven low. in the rt1425, a1425a, rt1460, a1460a, rt14100, and a14100a devices, unused i/o pins are automatically tristated. ioclk dedicated (hard-wired) i/o clock (input) not applicable for rt1020, a1020b, rt1280a and a1280a. ttl clock input for i/o modules. this input is directly wired to each i/o module, offering clock speeds independent of the number of i/o modules being driven. this pin can also be used as an i/o. iopcl dedicated (hard-wired) i/o preset/clear (input) not applicable for rt1020, a1020b, rt1280a and a1280a. ttl input for i/o pres et or clear. this global input is directly wired to the preset and clear inputs of all i/o registers. this pin func tions as an i/o when no i/o preset or clear macros are used. mode mode (input) the mode pin controls the use of diagnostic pins (dclk, pra, prb, sdi). when the mode pin is high, the special functions are active. when the mode pin is low, the pins function as i/os. to provide debugging capability, the mode pin should be terminated to gnd through a 10 k ? resistor so that the mode pin can be pulled high when required. nc no connection this pin is not connected to circuitry within the device. pra, i/o probe a (output) the probe a pin is used to output data from any user- defined design node within the device. this independent diagnostic pin can be used in conjunction with the probe b pin to allow real-time diagnostic output of any signal path within the device. the probe a pin can be used as a user-defined i/o when verification has been completed. the pin?s probe capabilities can be permanently disabled to protect programmed design confidentiality. pra is accessible when the mode pin is high. this pin functions as an i/o when the mode pin is low. prb, i/o probe b (output) the probe b pin is used to output data from any user- defined design node within the device. this independent diagnostic pin can be used in conjunction with the probe a pin to allow real-time diagnostic output of any signal path within the device. the probe b pin can be used as a user-defined i/o when verification has been completed. the pin?s probe capabilities can be permanently disabled to protect programmed design confidentiality. prb is accessible when the mode pin is high. this pin functions as an i/o when the mode pin is low. sdi serial data input (input) serial data input for diagnostic probe and device programming. sdi is active when the mode pin is high. this pin functions as an i/o when the mode pin is low. v cc 5.0 v supply voltage high supply voltage. radtolerant fpgas v3.1 2-1 package pin assignments 84-pin cqfp figure 2-1 84-pin cqfp (top view) pin #1 index 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 84-pin cqfp 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 radtolerant fpgas 2-2 v3.1 84-pin cqfp pin number a1020b function rt1020 function 1ncnc 2i/oi/o 3i/oi/o 4i/oi/o 5i/oi/o 6i/oi/o 7gndgnd 8gndgnd 9i/oi/o 10 i/o i/o 11 i/o i/o 12 i/o i/o 13 i/o i/o 14 v cc v cc 15 v cc v cc 16 i/o i/o 17 i/o i/o 18 i/o i/o 19 i/o i/o 20 i/o i/o 21 i/o i/o 22 v cc v cc 23 i/o i/o 24 i/o i/o 25 i/o i/o 26 i/o i/o 27 i/o i/o 28 i/o i/o 29 gnd gnd 30 i/o i/o 31 i/o i/o 32 i/o i/o 33 i/o i/o 34 i/o i/o 35 v cc v cc 36 i/o i/o 37 i/o i/o 38 i/o i/o 39 i/o i/o 40 i/o i/o 41 i/o i/o 42 i/o i/o 43 i/o i/o 44 i/o i/o 45 i/o i/o 46 i/o i/o 47 i/o i/o 48 i/o i/o 49 gnd gnd 50 gnd gnd 51 i/o i/o 52 i/o i/o 53 clka, i/o clka, i/o 54 i/o i/o 55 mode mode 56 v cc v cc 57 v cc v cc 58 i/o i/o 59 i/o i/o 60 i/o i/o 61 sdi, i/o sdi, input 62 dclk, i/o dclk, input 63 pra, i/o pra, i/o 64 prb, i/o prb, i/o 65 i/o i/o 66 i/o i/o 67 i/o i/o 68 i/o i/o 69 i/o i/o 70 i/o i/o 84-pin cqfp pin number a1020b function rt1020 function 71 gnd gnd 72 i/o i/o 73 i/o i/o 74 i/o i/o 75 i/o i/o 76 i/o i/o 77 v cc v cc 78 i/o i/o 79 i/o i/o 80 i/o i/o 81 i/o i/o 82 i/o i/o 83 i/o i/o 84 i/o i/o 84-pin cqfp pin number a1020b function rt1020 function radtolerant fpgas v3.1 2-3 132-pin cqfp figure 2-2 132-pin cqfp (top view) 132-pin cqfp pin #1 index 132131130129128127126125124 107106105104103 102 101 100 34 35 36 37 38 39 40 41 42 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 92 93 94 95 96 97 98 99 33 32 31 30 29 28 27 26 25 8 7 6 5 4 3 2 1 radtolerant fpgas 2-4 v3.1 132-pin cqfp pin number a1425a function rt1425a function 1ncnc 2gndgnd 3 sdi, i/o sdi, i/o 4i/oi/o 5i/oi/o 6i/oi/o 7i/oi/o 8i/oi/o 9 mode mode 10 gnd gnd 11 v cc v cc 12 i/o i/o 13 i/o i/o 14 i/o i/o 15 i/o i/o 16 i/o i/o 17 i/o i/o 18 i/o i/o 19 i/o i/o 20 i/o i/o 21 i/o i/o 22 v cc v cc 23 i/o i/o 24 i/o i/o 25 i/o i/o 26 gnd gnd 27 v cc v cc 28 i/o i/o 29 i/o i/o 30 i/o i/o 31 i/o i/o 32 i/o i/o 33 i/o i/o 34 nc nc 35 i/o i/o 36 gnd gnd 37 i/o i/o 38 i/o i/o 39 i/o i/o 40 i/o i/o 41 i/o i/o 42 gnd gnd 43 v cc v cc 44 i/o i/o 45 i/o i/o 46 i/o i/o 47 i/o i/o 48 prb, i/o prb, i/o 49 i/o i/o 50 hclk, i/o hclk, i/o 51 i/o i/o 52 i/o i/o 53 i/o i/o 54 i/o i/o 55 i/o i/o 56 i/o i/o 57 i/o i/o 58 gnd gnd 59 v cc v cc 60 i/o i/o 61 i/o i/o 62 i/o i/o 63 i/o i/o 64 iopcl, i/o iopcl, i/o 65 gnd gnd 66 nc nc 67 nc nc 68 i/o i/o 69 i/o i/o 70 i/o i/o 132-pin cqfp pin number a1425a function rt1425a function 71 i/o i/o 72 i/o i/o 73 i/o i/o 74 gnd gnd 75 v cc v cc 76 i/o i/o 77 i/o i/o 78 v cc v cc 79 i/o i/o 80 i/o i/o 81 i/o i/o 82 i/o i/o 83 i/o i/o 84 i/o i/o 85 i/o i/o 86 i/o i/o 87 i/o i/o 88 i/o i/o 89 v cc v cc 90 gnd gnd 91 v cc v cc 92 gnd gnd 93 i/o i/o 94 i/o i/o 95 i/o i/o 96 i/o i/o 97 i/o i/o 98 ioclk, i/o ioclk, i/o 99 nc nc 100 nc nc 101 gnd gnd 102 i/o i/o 103 i/o i/o 104 i/o i/o 105 i/o i/o 132-pin cqfp pin number a1425a function rt1425a function radtolerant fpgas v3.1 2-5 106 gnd gnd 107 v cc v cc 108 i/o i/o 109 i/o i/o 110 i/o i/o 111 i/o i/o 112 i/o i/o 113 i/o i/o 114 i/o i/o 115 i/o i/o 116 clka, i/o clka, i/o 117 clkb, i/o clkb, i/o 118 pra, i/o pra, i/o 119 i/o i/o 120 i/o i/o 121 i/o i/o 122 gnd gnd 123 v cc v cc 124 i/o i/o 125 i/o i/o 126 i/o i/o 127 i/o i/o 128 i/o i/o 129 i/o i/o 130 i/o i/o 131 dclk, i/o dclk, i/o 132 nc nc 132-pin cqfp pin number a1425a function rt1425a function radtolerant fpgas 2-6 v3.1 172-pin cqfp figure 2-3 172-pin cqfp (top view) 172-pin cqfp pin #1 index 172 171 170 169 168 167 166 165 164 137 136 135 134 133 132 131 130 44 45 46 47 48 49 50 51 52 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 122 123 124 125 126 127 128 129 43 42 41 40 39 38 37 36 35 8 7 6 5 4 3 2 1 radtolerant fpgas v3.1 2-7 172-pin cqfp pin number a1280a function rt1280a function 1 mode mode 2i/oi/o 3i/oi/o 4i/oi/o 5i/oi/o 6i/oi/o 7gndgnd 8i/oi/o 9i/oi/o 10 i/o i/o 11 i/o i/o 12 v cc v cc 13 i/o i/o 14 i/o i/o 15 i/o i/o 16 i/o i/o 17 gnd gnd 18 i/o i/o 19 i/o i/o 20 i/o i/o 21 i/o i/o 22 gnd gnd 23 v cc v cc 24 v cc v cc 25 i/o i/o 26 i/o i/o 27 v cc v cc 28 i/o i/o 29 i/o i/o 30 i/o i/o 31 i/o i/o 32 gnd gnd 33 i/o i/o 34 i/o i/o 35 i/o i/o 36 i/o i/o 37 gnd gnd 38 i/o i/o 39 i/o i/o 40 i/o i/o 41 i/o i/o 42 i/o i/o 43 i/o i/o 44 i/o i/o 45 i/o i/o 46 i/o i/o 47 i/o i/o 48 i/o i/o 49 i/o i/o 50 v cc v cc 51 i/o i/o 52 i/o i/o 53 i/o i/o 54 i/o i/o 55 gnd gnd 56 i/o i/o 57 i/o i/o 58 i/o i/o 59 i/o i/o 60 i/o i/o 61 i/o i/o 62 i/o i/o 63 i/o i/o 64 i/o i/o 65 gnd gnd 66 v cc v cc 67 i/o i/o 68 i/o i/o 69 i/o i/o 70 i/o i/o 172-pin cqfp pin number a1280a function rt1280a function 71 i/o i/o 72 i/o i/o 73 i/o i/o 74 i/o i/o 75 gnd gnd 76 i/o i/o 77 i/o i/o 78 i/o i/o 79 i/o i/o 80 v cc v cc 81 i/o i/o 82 i/o i/o 83 i/o i/o 84 i/o i/o 85 i/o i/o 86 i/o i/o 87 i/o i/o 88 i/o i/o 89 i/o i/o 90 i/o i/o 91 i/o i/o 92 i/o i/o 93 i/o i/o 94 i/o i/o 95 i/o i/o 96 i/o i/o 97 i/o i/o 98 gnd gnd 99 i/o i/o 100 i/o i/o 101 i/o i/o 102 i/o i/o 103 gnd gnd 104 i/o i/o 105 i/o i/o 172-pin cqfp pin number a1280a function rt1280a function radtolerant fpgas 2-8 v3.1 106 gnd gnd 107 v cc v cc 108 gnd gnd 109 v cc v cc 110 v cc v cc 111 i/o i/o 112 i/o i/o 113 v cc v cc 114 i/o i/o 115 i/o i/o 116 i/o i/o 117 i/o i/o 118 gnd gnd 119 i/o i/o 120 i/o i/o 121 i/o i/o 122 i/o i/o 123 gnd gnd 124 i/o i/o 125 i/o i/o 126 i/o i/o 127 i/o i/o 128 i/o i/o 129 i/o i/o 130 i/o i/o 131 sdi, i/o sdi, i/o 132 i/o i/o 133 i/o i/o 134 i/o i/o 135 i/o i/o 136 v cc v cc 137 i/o i/o 138 i/o i/o 139 i/o i/o 140 i/o i/o 172-pin cqfp pin number a1280a function rt1280a function 141 gnd gnd 142 i/o i/o 143 i/o i/o 144 i/o i/o 145 i/o i/o 146 i/o i/o 147 i/o i/o 148 pra, i/o pra, i/o 149 i/o i/o 150 clka, i/o clka, i/o 151 v cc v cc 152 gnd gnd 153 i/o i/o 154 clkb, i/o clkb, i/o 155 i/o i/o 156 prb, i/o prb, i/o 157 i/o i/o 158 i/o i/o 159 i/o i/o 160 i/o i/o 161 gnd gnd 162 i/o i/o 163 i/o i/o 164 i/o i/o 165 i/o i/o 166 v cc v cc 167 i/o i/o 168 i/o i/o 169 i/o i/o 170 i/o i/o 171 dclk, i/o dclk, i/o 172 i/o i/o 172-pin cqfp pin number a1280a function rt1280a function radtolerant fpgas v3.1 2-9 196-pin cqfp figure 2-4 196-pin cqfp (top view) 196-pin cqfp pin #1 index 196 195 194 193 192 191 190 189 188 155 154 153 152 151 150 149 148 50 51 52 53 54 55 56 57 58 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 140 141 142 143 144 145 146 147 49 48 47 46 45 44 43 42 41 8 7 6 5 4 3 2 1 radtolerant fpgas 2-10 v3.1 196-pin cqfp pin number a1460a function rt1460a function 1gndgnd 2 sdi, i/o sdi, i/o 3i/oi/o 4i/oi/o 5i/oi/o 6i/oi/o 7i/oi/o 8i/oi/o 9i/oi/o 10 i/o i/o 11 mode mode 12 v cc v cc 13 gnd gnd 14 i/o i/o 15 i/o i/o 16 i/o i/o 17 i/o i/o 18 i/o i/o 19 i/o i/o 20 i/o i/o 21 i/o i/o 22 i/o i/o 23 i/o i/o 24 i/o i/o 25 i/o i/o 26 i/o i/o 27 i/o i/o 28 i/o i/o 29 i/o i/o 30 i/o i/o 31 i/o i/o 32 i/o i/o 33 i/o i/o 34 i/o i/o 35 i/o i/o 36 i/o i/o 37 gnd gnd 38 v cc v cc 39 v cc v cc 40 i/o i/o 41 i/o i/o 42 i/o i/o 43 i/o i/o 44 i/o i/o 45 i/o i/o 46 i/o i/o 47 i/o i/o 48 i/o i/o 49 i/o i/o 50 i/o i/o 51 gnd gnd 52 gnd gnd 53 i/o i/o 54 i/o i/o 55 i/o i/o 56 i/o i/o 57 i/o i/o 58 i/o i/o 59 v cc v cc 60 i/o i/o 61 i/o i/o 62 i/o i/o 63 i/o i/o 64 gnd gnd 65 i/o i/o 66 i/o i/o 67 i/o i/o 68 i/o i/o 69 i/o i/o 70 i/o i/o 196-pin cqfp pin number a1460a function rt1460a function 71 i/o i/o 72 i/o i/o 73 i/o i/o 74 i/o i/o 75 prb, i/o prb, i/o 76 i/o i/o 77 hclk, i/o hclk, i/o 78 i/o i/o 79 i/o i/o 80 i/o i/o 81 i/o i/o 82 i/o i/o 83 i/o i/o 84 i/o i/o 85 i/o i/o 86 gnd gnd 87 i/o i/o 88 i/o i/o 89 i/o i/o 90 i/o i/o 91 i/o i/o 92 i/o i/o 93 i/o i/o 94 v cc v cc 95 i/o i/o 96 i/o i/o 97 i/o i/o 98 gnd gnd 99 i/o i/o 100 iopcl, i/o iopcl, i/o 101 gnd gnd 102 i/o i/o 103 i/o i/o 104 i/o i/o 105 i/o i/o 196-pin cqfp pin number a1460a function rt1460a function radtolerant fpgas v3.1 2-11 106 i/o i/o 107 i/o i/o 108 i/o i/o 109 i/o i/o 110 v cc v cc 111 v cc v cc 112 gnd gnd 113 i/o i/o 114 i/o i/o 115 i/o i/o 116 i/o i/o 117 i/o i/o 118 i/o i/o 119 i/o i/o 120 i/o i/o 121 i/o i/o 122 i/o i/o 123 i/o i/o 124 i/o i/o 125 i/o i/o 126 i/o i/o 127 i/o i/o 128 i/o i/o 129 i/o i/o 130 i/o i/o 131 i/o i/o 132 i/o i/o 133 i/o i/o 134 i/o i/o 135 i/o i/o 136 i/o i/o 137 v cc v cc 138 gnd gnd 139 gnd gnd 140 v cc v cc 196-pin cqfp pin number a1460a function rt1460a function 141 i/o i/o 142 i/o i/o 143 i/o i/o 144 i/o i/o 145 i/o i/o 146 i/o i/o 147 i/o i/o 148 ioclk, i/o ioclk, i/o 149 gnd gnd 150 i/o i/o 151 i/o i/o 152 i/o i/o 153 i/o i/o 154 i/o i/o 155 v cc v cc 156 i/o i/o 157 i/o i/o 158 i/o i/o 159 i/o i/o 160 i/o i/o 161 i/o i/o 162 gnd gnd 163 i/o i/o 164 i/o i/o 165 i/o i/o 166 i/o i/o 167 i/o i/o 168 i/o i/o 169 i/o i/o 170 i/o i/o 171 i/o i/o 172 clka, i/o clka, i/o 173 clkb, i/o clkb, i/o 174 pra, i/o pra, i/o 175 i/o i/o 196-pin cqfp pin number a1460a function rt1460a function 176 i/o i/o 177 i/o i/o 178 i/o i/o 179 i/o i/o 180 i/o i/o 181 i/o i/o 182 i/o i/o 183 gnd gnd 184 i/o i/o 185 i/o i/o 186 i/o i/o 187 i/o i/o 188 i/o i/o 189 v cc v cc 190 i/o i/o 191 i/o i/o 192 i/o i/o 193 gnd gnd 194 i/o i/o 195 i/o i/o 196 dclk, i/o dclk, i/o 196-pin cqfp pin number a1460a function rt1460a function radtolerant fpgas 2-12 v3.1 256-pin cqfp figure 2-5 256-pin cqfp (top view) 256-pin cqfp pin #1 index 256 255 254 253 252 251 250 249 248 200 199 198 197 196 195 194 193 65 66 67 68 69 70 71 72 73 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 185 186 187 188 189 190 191 192 64 63 62 61 60 59 58 57 56 8 7 6 5 4 3 2 1 radtolerant fpgas v3.1 2-13 256-pin cqfp pin number a14100a function rt14100a function 1gndgnd 2 sdi, i/o sdi, i/o 3i/oi/o 4i/oi/o 5i/oi/o 6i/oi/o 7i/oi/o 8i/oi/o 9i/oi/o 10 i/o i/o 11 mode mode 12 i/o i/o 13 i/o i/o 14 i/o i/o 15 i/o i/o 16 i/o i/o 17 i/o i/o 18 i/o i/o 19 i/o i/o 20 i/o i/o 21 i/o i/o 22 i/o i/o 23 i/o i/o 24 i/o i/o 25 i/o i/o 26 i/o i/o 27 i/o i/o 28 v cc v cc 29 gnd gnd 30 v cc v cc 31 gnd gnd 32 i/o i/o 33 i/o i/o 34 i/o i/o 35 i/o i/o 36 i/o i/o 37 i/o i/o 38 i/o i/o 39 i/o i/o 40 i/o i/o 41 i/o i/o 42 i/o i/o 43 i/o i/o 44 i/o i/o 45 i/o i/o 46 v cc v cc 47 i/o i/o 48 i/o i/o 49 i/o i/o 50 i/o i/o 51 i/o i/o 52 i/o i/o 53 i/o i/o 54 i/o i/o 55 i/o i/o 56 i/o i/o 57 i/o i/o 58 i/o i/o 59 gnd gnd 60 i/o i/o 61 i/o i/o 62 i/o i/o 63 i/o i/o 64 i/o i/o 65 i/o i/o 66 i/o i/o 67 i/o i/o 68 i/o i/o 69 i/o i/o 70 i/o i/o 256-pin cqfp pin number a14100a function rt14100a function 71 i/o i/o 72 i/o i/o 73 i/o i/o 74 i/o i/o 75 i/o i/o 76 i/o i/o 77 i/o i/o 78 i/o i/o 79 i/o i/o 80 i/o i/o 81 i/o i/o 82 i/o i/o 83 i/o i/o 84 i/o i/o 85 i/o i/o 86 i/o i/o 87 i/o i/o 88 i/o i/o 89 i/o i/o 90 prb, i/o prb, i/o 91 gnd gnd 92 v cc v cc 93 gnd gnd 94 v cc v cc 95 i/o i/o 96 hclk, i/o hclk, i/o 97 i/o i/o 98 i/o i/o 99 i/o i/o 100 i/o i/o 101 i/o i/o 102 i/o i/o 103 i/o i/o 104 i/o i/o 105 i/o i/o 256-pin cqfp pin number a14100a function rt14100a function radtolerant fpgas 2-14 v3.1 106 i/o i/o 107 i/o i/o 108 i/o i/o 109 i/o i/o 110 gnd gnd 111 i/o i/o 112 i/o i/o 113 i/o i/o 114 i/o i/o 115 i/o i/o 116 i/o i/o 117 i/o i/o 118 i/o i/o 119 i/o i/o 120 i/o i/o 121 i/o i/o 122 i/o i/o 123 i/o i/o 124 i/o i/o 125 i/o i/o 126 i/o i/o 127 iopcl, i/o iopcl, i/o 128 gnd gnd 129 i/o i/o 130 i/o i/o 131 i/o i/o 132 i/o i/o 133 i/o i/o 134 i/o i/o 135 i/o i/o 136 i/o i/o 137 i/o i/o 138 i/o i/o 139 i/o i/o 140 i/o i/o 256-pin cqfp pin number a14100a function rt14100a function 141 v cc v cc 142 i/o i/o 143 i/o i/o 144 i/o i/o 145 i/o i/o 146 i/o i/o 147 i/o i/o 148 i/o i/o 149 i/o i/o 150 i/o i/o 151 i/o i/o 152 i/o i/o 153 i/o i/o 154 i/o i/o 155 i/o i/o 156 i/o i/o 157 i/o i/o 158 gnd gnd 159 v cc v cc 160 gnd gnd 161 v cc v cc 162 i/o i/o 163 i/o i/o 164 i/o i/o 165 i/o i/o 166 i/o i/o 167 i/o i/o 168 i/o i/o 169 i/o i/o 170 i/o i/o 171 i/o i/o 172 i/o i/o 173 i/o i/o 174 v cc v cc 175 gnd gnd 256-pin cqfp pin number a14100a function rt14100a function 176 gnd gnd 177 i/o i/o 178 i/o i/o 179 i/o i/o 180 i/o i/o 181 i/o i/o 182 i/o i/o 183 i/o i/o 184 i/o i/o 185 i/o i/o 186 i/o i/o 187 i/o i/o 188 ioclk, i/o ioclk, i/o 189 gnd gnd 190 i/o i/o 191 i/o i/o 192 i/o i/o 193 i/o i/o 194 i/o i/o 195 i/o i/o 196 i/o i/o 197 i/o i/o 198 i/o i/o 199 i/o i/o 200 i/o i/o 201 i/o i/o 202 i/o i/o 203 i/o i/o 204 i/o i/o 205 i/o i/o 206 i/o i/o 207 i/o i/o 208 i/o i/o 209 i/o i/o 210 i/o i/o 256-pin cqfp pin number a14100a function rt14100a function radtolerant fpgas v3.1 2-15 211 i/o i/o 212 i/o i/o 213 i/o i/o 214 i/o i/o 215 i/o i/o 216 i/o i/o 217 i/o i/o 218 i/o i/o 219 clka, i/o clka, i/o 220 clkb, i/o clkb, i/o 221 v cc v cc 222 gnd gnd 223 v cc v cc 224 gnd gnd 225 pra, i/o pra, i/o 226 i/o i/o 227 i/o i/o 228 i/o i/o 229 i/o i/o 230 i/o i/o 231 i/o i/o 232 i/o i/o 233 i/o i/o 234 i/o i/o 235 i/o i/o 236 i/o i/o 237 i/o i/o 238 i/o i/o 239 i/o i/o 240 gnd gnd 241 i/o i/o 242 i/o i/o 243 i/o i/o 244 i/o i/o 245 i/o i/o 256-pin cqfp pin number a14100a function rt14100a function 246 i/o i/o 247 i/o i/o 248 i/o i/o 249 i/o i/o 250 i/o i/o 251 i/o i/o 252 i/o i/o 253 i/o i/o 254 i/o i/o 255 i/o i/o 256 dclk, i/o dclk, i/o 256-pin cqfp pin number a14100a function rt14100a function radtolerant fpgas v3.1 3-1 datasheet information list of changes the following table lists critical changes that were made in the current version of the document. datasheet categories in order to provide the latest information to designers, some datasheets are published before data has been fully characterized. datasheets are desi gnated as "product brief," "advance d," "production," and "datasheet supplement." the definitions of these categories are as follows: product brief the product brief is a summarized version of a datasheet (advanced or production) containing general product information. this brief gives an overview of specific device and family information. advanced this datasheet version contains initial estimated information based on simulation, other products, devices, or speed grades. this information can be used as estimates, but not for production. unmarked (production) this datasheet version contains informat ion that is considered to be final. datasheet supplement the datasheet supplement gives specific device information for a derivative family that differs from the general family datasheet. the supplement is to be used in conjunction with the datasheet to obtain more detailed information and for specifications th at do not differ between the two families. export administration regulations (ear) or international traffic in arms regulations (itar) the product described in this datasheet could be subject to either the export administration regulations (ear) or in some cases the international traffic in arms regulations (itar). they could require an approved export license prior to export from the united states. an export includes release of product or disclosure of technology to a foreign national inside or outside the united states. previous version changes in current version (v 3 .1 ) page v3.0 the following pins changed in the "84-pin cqfp" table: pin 61 change to sdi, input for the rt1020 device. pin 62 change to dclk, input for the rt1020 device. 2-2 the following pins changed in the "256-pin cqfp" table: pin 124 change to i/o for the a14100a and rt14100a devices. pin 127 changed to iopcl for the a14100a and rt14100a devices. 2-14 5172139-4/10.04 http://www.actel.com actel and the actel logo are registered trademarks of actel corporation. all other trademarks are the property of their owners. actel corporation 2061 stierlin court mountain view, ca 94043-4655 usa phone 650.318.4200 fax 650.318.4600 actel europe ltd. dunlop house, riverside way camberley, surrey gu15 3yl united kingdom phone +44 (0)1276 401 450 fax +44 (0)1276 401 490 actel japan exos ebisu bldg. 4f 1-24-14 ebisu shibuya-ku tokyo 150 japan phone +81.03.3445.7671 fax +81.03.3445.7668 actel hong kong 39th floor, on e pacific place 88 queensway, admiralty hong kong phone +852.227.35712 fax +852.227.35999 |
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